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IEC 62530 Ed.3.0 Edition 07/2021
SystemVerilog - Unified Hardware Design, Specification, and Verification Language
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  • 432 / copy
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Abstract

IEC 62530:2021(E) provides the definition of the language syntax and semantics for the IEEE 1800™ SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.
This edition corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
This publication has the status of a double logo IEEE/IEC standard.

Status

Standard - Active

Origin

Technical Committee :
91 : Electronics assembly technology

Implementation

start of the vote on the project      date of ratification (dor)   
end of the vote on the project      date of anouncement (doa)   
start of the vote on the final project      date of publication (dop)   
end of the vote on the final project      date of withdrawal (dow)   


Publication Official Journal
of the Grand-Duchy of Luxembourg
Reference

Relations

Relations to older standards
IEC 62530 Ed. 2.0

International Classification for Standards (ICS codes) :

25.040.01 : Industrial automation systems in general
35.060 : Languages used in information technology

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