magnifying icon Basket
1 item ^

Basket is empty
Login

Login

LOGGED AS

Help

Satisfaction enquiry

SATISFACTION ENQUIRY

Newsletter

Free of charge lifelong learning "Standardization"

FREE OF CHARGE LIFELONG LEARNING "STANDARDIZATION"

Standardisation

Draft standards in public enquiry

DRAFT STANDARDS IN PUBLIC ENQUIRY

Standards organizations

STANDARDS ORGANIZATIONS

  • National standards

  • European standards

  • International standards


Deliverable

 
Free preview
Price
Language
 
IEC 61691-6 Ed. 1.0 Edition 12/2009
Behavioural languages - Part 6: VHDL Analog and Mixed-Signal Extensions
  •   
  •  
  • 432 / copy
  •  
 

Abstract

IEC 61691-6:2009(E) Defines IEC 61691-6/IEEE Std 1076.1 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. The language, also informally known as VHDLAMS, is built on the IEC 61691-1-1/IEEE 1076 (VHDL) language and extends it to provide capabilities of writing and simulating analog and mixed-signal models.

Status

Standard - Active

Origin

Technical Committee :
91 : Electronics assembly technology

Implementation

start of the vote on the project      date of ratification (dor)   
end of the vote on the project      date of anouncement (doa)   
start of the vote on the final project      date of publication (dop)   
end of the vote on the final project      date of withdrawal (dow)   


Publication Official Journal
of the Grand-Duchy of Luxembourg
Reference

Relations

Evolutions
IEC 60951-3 Ed.3.0 RLV
IEC 61691-6 Ed.2.0

International Classification for Standards (ICS codes) :

25.040 : Industrial automation systems
35.060 : Languages used in information technology

magnifying icon Basket
1 item ^

Basket is empty


Warning:
DIN standards can be downloaded only once! After downloading, they are no longer available in the eLibrary.
Begin download?