Abstract
IEC 61691-1-1:2011(E) Revises and enhances the VHDL language reference manual (LRM) by including a standard C language interface specification. The VHDL language was defined for use in the design and documentation of electronics systems. It is revised to incorporate capabilities that improve the language's usefulness for its intended purpose as well as extend it to address design verification methodologies that have developed in industry. These new design and verification capabilities are required to ensure VHDL remains relevant and valuable for use in electronic systems design and verification. Incorporation of previously separate, but related standards, simplifies the maintenance of the specifications. This publication has the status of a double logo IEEE/IEC standard.
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