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Standardisation

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IEC 62530 Ed. 1.0 Edition 11/2007
Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language
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  • 432 / copy
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Abstract

Specifies extensions for a higher level of abstraction for modeling and verification with the Verilog hardware description language (HDL). This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI)>

Status

Standard - Superseded

Origin

Technical Committee :
93 : Design automation

Implementation

start of the vote on the project      date of ratification (dor)   
end of the vote on the project      date of anouncement (doa)   
start of the vote on the final project      date of publication (dop)   
end of the vote on the final project      date of withdrawal (dow)   


Publication Official Journal
of the Grand-Duchy of Luxembourg
Reference

Relations

Evolutions
IEC 60951-3 Ed.3.0 RLV

International Classification for Standards (ICS codes) :

25.040 : Industrial automation systems

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