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IEC 62530-2 Ed.1.0 Edition 07/2021
SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual
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  • 432 / copy
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Abstract

IEC 62530-2:2021(E) establishes the Universal Verification Methodology (UVM), a set of application programming
interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™. This publication has the status of a double logo IEC/IEEE standard.

Status

Standard - Active

Origin

Technical Committee :
91 : Electronics assembly technology

Implementation

start of the vote on the project      date of ratification (dor)   
end of the vote on the project      date of anouncement (doa)   
start of the vote on the final project      date of publication (dop)   
end of the vote on the final project      date of withdrawal (dow)   


Publication Official Journal
of the Grand-Duchy of Luxembourg
Reference

Relations

Evolutions
IEC 60951-3 Ed.3.0 RLV
IEC 62530-2 Ed.2.0

International Classification for Standards (ICS codes) :

25.040.01 : Industrial automation systems in general
35.060 : Languages used in information technology

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